1. Field of the Invention
This invention relates to data handling arrays and especially but not exclusively to fault tolerant data processing arrays.
2. Description of Related Art
In order to provide a computer apparatus capable of processing data at a very high speed, it has been proposed to provide the computer circuitry in the form of a plurality of separate data processing means which operate simultaneously to perform different parts of the processing required at the same time. In order to make the best use of the processing speed of the individual processing means it is desirable to have very high speed communication between the processing means. Very many short interconnections are required between the processing means to provide the high speed communication and one way of achieving such interconnections is to include all the processing means in a single integrated circuit--formed on a slice of semi-conductor material as a so-called wafer scale integrated circuit. An advantage of such a construction is that the entire slice can be processed at the same time, thereby keeping to a minimum the cost of manufacture of the system. Most conveniently the processing means formed on the slice each contain substantially the same circuit with a processor and memory The disadvantage with such an arrangement lies in the fact that dislocations due to the presence of impurities can occur in the crystal structure of the semi-conductor material of which the slice is made and such dislocations can prevent the processing means from functioning properly. The number of such dislocations depends on the area of semi-conductor material involved.
Therefore, although acceptable yields can be obtained of integrated circuits using for example a 10 mm square chip of silicon, because there would be about 450 such squares on a 5 inch diameter slice, failure of 50 of these individual circuits to work properly may be regarded as acceptable since nearly 90 percent of the production did work.
If, however, all of these circuits are interconnected to form a single unit, some means has to be found of identifying those circuits which do not work and providing communication between the circuits which do work and leaving out those which do not work, so that a functional entity is obtained. Various proposals have been made for testing of individual circuits and then for providing interconnections between only those circuits which have been found to work This technique suffers from the disadvantage that the testing of all of the individual circuits can be time-consuming and also that at least temporary wiring must be provided to enable the results of the tests to be derived from the individual circuits and further wiring then added so that those circuits which do not work can be bypassed.